This page describes a cpp bench, which is used to verify a parallel fifo, using verilator.

1. In order to practice cpp (c++) verification benches, with system verilog DPI, using a verilog DUT, I decided to download verilator and do some self study exercises.
   


2. This cpp bench is based on parallel fifo. Both cases are used as simple exercises to gain some experience with verilator.
   The stimuli drive is done differently. Instead of dot notation access
   
   gen(entry);
   pipe_fifo->rd = entry.rd;
   pipe_fifo->wr = entry.wr;
   
   a DPI task is used.
   
   gen(entry);
   //drive using c2v DPI function
   t_gen_stim(entry.rd, entry.wr);
   



3. The DUT (parallel FIFO) is now instantiated under a system verilog tool. The tool gets its clock and reset in the usual way from verilator. The read write commands are now driven by a task:
   
   ...
     initial begin
       Trd=1'b0;
       Twr=1'b0;
     end
     export "DPI-C" task t_gen_stim;
     task t_gen_stim;
       input bit trd;
       input bit twr;
       $display("task drive %d %d at %d", trd, twr, $time);
       Trd=trd;
       Twr=twr;
     endtask
     reg Trd, Twr;
   ...
   



4. To monitor a signal change the opposite is required. SV checks the error flag ( always block), when it changes, it sends data to cpp via DPI.
   
     //monitor fifo errors v2c DPI function
     import "DPI-C" function integer f_ferr(integer ferr);
   ...
     always @ (posedge clk) begin
       ferrq <= ferr;
       if(ferrq != ferr) begin
         $display("sv mon ferr %d at %d %d", ferr, ferrq, $time);
         f_ferr(ferr);
       end
     end
   
   In the cpp bench:
   
   
   1. int f_ferr(int ferr) {
      
   2.   cout << "sim gen ferr " << ferr << " time is " << main_time << endl; // Read a output
      
   3. }
      
   4. 
      
   5. int main(int argc, char** argv) {
      
   6. ...
      
   
   A word about seed. I use rand() to randomize write and read access. The seed is either taken from command line, or a random one is used:
   
   
   1. void gen(Entry& entry) {
   2.   static int fifo_level;
   4.   entry.rd=0;
   5.   entry.wr=0;
   6.   if(entry.ti >= (41+delta)) {
   7.     if(entry.fe == 1 && fifo_level > 0) entry.rd=rand() % 2;
   8.     if(entry.ff == 0 && fifo_level < 4) entry.wr=rand() % 2;
   9.   }
   10. ...
   11. int main(int argc, char** argv) {
   12.   unsigned int c_seed;
   13.   if(argc == 1) {
   14.     c_seed=time(NULL);
   15.   }
   16.   else {
   17.     c_seed=atoi(argv[1]);
   18.     cout << "sim seed is NOT random !!!!" << endl;
   19.   }
   20.   srand (c_seed);
   21.   cout << "sim seed is " << c_seed << endl;
   22. ...



5. The compile and run script had be changed too
   
   
   1. #!/bin/bash
      
   2. 
      
   3. if [ -e obj_dir/Vpipe_fifo_tool ] ; then
      
   4.   rm obj_dir/Vpipe_fifo_tool
      
   5. fi
      
   6. #--debug -CFLAGS -g
      
   7. clear;verilator -CFLAGS -g --trace --trace-depth 2 -sv --cc pipe_fifo_tool.sv --exe sim_main.cpp
      
   8. cd obj_dir
      
   9. make -j -f Vpipe_fifo_tool.mk Vpipe_fifo_tool && echo "make ended ok"
      

Home	some memory VHDL models my first experience with verilator.