This page describes a cpp bench, which is used to verify a parallel fifo, using verilator.

1. In order to practice cpp (c++) verification benches, with system verilog DPI, using a verilog DUT, I decided to download verilator and do some self study exercises.
   


2. This cpp bench is based on an hierarchical Design Under Test and a time management cpp bench. Both cases are used as simple exercises to gain some experience with verilator.
   In addition to time management and VCD wave trace, this example also generates stimuli to the Design Under Test.
   This page describes the coding of a data stimuli generator, using verilator. More, complex benches, will come later.



3. The Design Under Test is a FIFO. The data path of the FIFO is N (4 in this example) 8 bits flip-flops connected in parallel (direct connect between Qn-1 to Dn) to achieve the fastest FIFO on an FPGA.
   The control is also based on N 1 bit flip flops connected as shift register. The full and empty flags as well as other control is taken from this shift register. All outputs are registered to farther facilitate timing in an FPGA.
   
   
   



4. The cpp bench is shown below. The changes, stimuli drive and generation, from previous example are marked. The DUT signals are accessed using verilator's pointer signal access (entry.fe=pipe_fifo->fe).
   
   
   1. #include "Vpipe_fifo.h"
   2. #include "verilated.h"
   4. //vcd traces
   5. #include "verilated_vcd_c.h"
   7. //cout
   8. #include <iostream>
   10. Vpipe_fifo *pipe_fifo; // Instantiation of module
   12. unsigned int main_time = 0; // Current simulation time
   14. double sc_time_stamp () { // Called by $time in Verilog
   15.   return main_time;
   16. }
   18. typedef struct _Entry{
   19.   unsigned int ti;
   20.   unsigned char rd;
   21.   unsigned char wr;
   22.   unsigned char fe;
   23.   unsigned char ff;
   24. } Entry;
   26. void gen(Entry& entry) {
   27.   entry.rd=0;
   28.   entry.wr=0;
   29.   if(entry.ti == 42) {
   30.     entry.rd=0;
   31.     entry.wr=1;
   32.   }
   33. }
   35. int main(int argc, char** argv) {
   36.   Verilated::commandArgs(argc, argv);
   37.   pipe_fifo = new Vpipe_fifo;
   39.   //vcd traces
   40.   Verilated::traceEverOn(true);
   41.   VerilatedVcdC* tfp = new VerilatedVcdC;
   42.   pipe_fifo->trace (tfp, 99);
   43.   tfp->open ("obj_dir/simx.vcd");
   45.   pipe_fifo->rst = 1;
   46.   pipe_fifo->rd = 0;
   47.   pipe_fifo->wr = 0;
   48.   pipe_fifo->DI = 16;
   50.   Entry entry;
   52.   while (!Verilated::gotFinish()) {
   53.     if (main_time > 10) {
   54.       pipe_fifo->rst = 0; // Deassert reset
   55.     }
   56.     if ((main_time % 10) == 1) {
   57.       pipe_fifo->clk = 1; // Toggle clock
   58.     }
   59.     if ((main_time % 10) == 6) {
   60.       pipe_fifo->clk = 0;
   61.     }
   63.     if (((main_time-1) % 10) == 1) {
   64.       //cout << "sim gen :time is " << main_time << endl; // Read a output
   65.       entry.ti=main_time;
   66.       entry.fe=pipe_fifo->fe;
   67.       entry.ff=pipe_fifo->ff;
   68.       gen(entry);
   69.       pipe_fifo->rd = entry.rd;
   70.       pipe_fifo->wr = entry.wr;
   71.     }
   73.     pipe_fifo->eval(); // Evaluate model
   75.     if(main_time > 200) break;
   76.     main_time++; // Time passes...
   77.     tfp->dump (main_time);
   78.   } //while
   79.   cout << "sim end :time is " << main_time << endl; // Read a output
   81.   tfp->close();
   82.   delete pipe_fifo;
   83.   exit(0);
   84. }



5. The design is compiled and run by the following script:
   
   
   1. #!/bin/bash
   3. if [ -e obj_dir/Vpipe_fifo ] ; then
   4.   rm obj_dir/Vpipe_fifo
   5. fi
   6. clear;/usr/bin/verilator --trace --trace-depth 1 --cc pipe_fifo.v --exe sim_main.cpp
   7. #sed -i "s/VERILATOR_ROOT = \/usr\/bin/VERILATOR_ROOT = \/usr\/share\/verilator/" obj_dir/Vpipe_fifo.mk
   8. cd obj_dir
   9. make -j -f Vpipe_fifo.mk Vpipe_fifo && echo "make ended ok"
   
   Regression is run by the following script. An error is detected if ERROR is found or sim end okay is not found.
   
   
   1. #!/bin/bash
   3. for i in {1..50000} ; do
   4.   if [ -e run_reg.log ] ; then
   5.     rm -f run_reg.log
   6.   fi
   7.   seed=$RANDOM
   8.   cmd="./obj_dir/Vpipe_fifo_tool "$seed" > run_reg.log"
   9.   eval $cmd
   11.   grep ERROR run_reg.log >& /dev/null
   12.   if [ $? -eq 0 ] ; then
   13.     cmd="cp run_reg.log run_reg_"$seed".log"
   14.     eval $cmd
   15.   else
   16.     grep "sim end.*okay" run_reg.log >& /dev/null
   17.     if [ $? -eq 1 ] ; then
   18.       cmd="cp run_reg.log run_reg_"$seed".log"
   19.       eval $cmd
   20.     fi
   21.   fi
   22. done

Home	some memory VHDL models my first experience with verilator.