ASIC/FPGA Design and Verification Out Source Services

This project is to test my concept of how to deal with asynchronous serial communication. The PHY is my design and so is the test bench to control it. The rest is taken from free stuff, which is available on the net.

1. The HDL code which is used is verilog. This is because the usb function from open core, Open Cores, is written in verilog.
2. The core uses a micro-processor for control. I used 8051 from http://www.cs.ucr.edu/~dalton/i8051/i8051syn. The VHDL code has been translated to verilog to avoid mix languages simulation. The cpu is also slightly modified to be able to use XILINX memories: for ROM I use ROM256X1 and for RAM RAM128X1S_1.
3. The simulator, which I use, is ICARUS: Free VERILOG simulator
4. The following pdf files shows a block diagram of the USB_1: Block Diagram
5. The PHY block diagram is given in the next pdf file: PHY Block Diagram

As said before the 8051 and USB functions are free stuff from the web and will not be described in this document. This document will only explain the modifications, which I made to these modules. The PHY will be described in detail.

1. The PHY connection to the USB function is described in PHY connection to USB function
2. For USB PHY description please enter: The USB PHY top
3. For USB PHY description please enter: The USB PHY top
4. A word about the USB 1.1 verification:
   The design uses kind of majority vote to on the receive side. It uses 48 MHz clock to extract data from a differential input lines at 12MHz. The issue in this simulation is to generate jitter at the input and see how design copes with it. It must be according specification or you will get errors at the receive.
   Another issue is that sometimes we need to add metastability checks to our verification environment. We usually replace the two flip-flops module with a model for simulation, where we randomly respond after one or two cycles. This model, however, is not good for the USB 1.1. When I did that in addition to the jitter injection, the receiver failed in some cases. The model has to be smarter and do randomly insert errors on the edges or the majority vote will fail.

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