ASIC/FPGA Design and Verification Out Source Services

CPU 8051 translation from VHDL to verilog. I used 8051 from http://www.cs.ucr.edu/~dalton/i8051/i8051syn The VHDL code has been translated to verilog. The cpu is also slightly modified to be able to use XILINX memories.

1. Design General: The design is translated from a VHDL dalton project http://www.cs.ucr.edu/~dalton/i8051/i8051syn.


2. Design Area: Consumes only 324 Flip-Flops.


3. Design Speed: 50MHz for a xc4vlx25-10 XILINX device.


4. Synthesized to XILINX: synthesis scripts


5. Memories suited for XILINX device for small code (ROM256X1 and RAM128X1S_1).


6. Set of scripts to convert between assembly to XILINX defparam u_rom0.INIT=256'h000000...


7. Script to compile and simulated with free icarus verilog simulator. verilog compilation script


8. verilog code


9. When it comes for generating the hex file of the assembly code, I strongly recommend to add remarks with the code itself:

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An extension to the example from cadance of producer consumer.