ASIC/FPGA Design and Verification Out Source Services

usb reset

The specification defines the following as reset: "D+ and D- VOL (max) for 10ms". This a way too long to simulate, so in order to make it easier for debug, I put a much smaller value ...
Pinhas

//10mSec x 48 MHz = 480000 = 0x75300
//10uSec x 48 MHz = 480 = 0x1e0
reg [8:0] cntq;
wire [8:0] cnti;
reg usb_rst;
wire usb_rsti;
assign usb_rsti=
(!usb_rst && cntq == 9'h1e0) || (usb_rst && sie0);
...

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