ASIC/FPGA Design and Verification Out Source Services

The following describes the assorted blocks of the receive top file.

1. The data first goes to u_rx_sync, which synchronizes the USB data lines. The data is simply sampled twice. The synchronizer has an optional model for simulation to better describe the meta-stable issues.
2. Than the data goes to the module rx_da. This module the data plus and SIE0. Its output is a serial stream of data NRZI encoded and without bit stuff. The outputs are valid, dv, and data, do. There is also a phase error count. If I can not figure out the data, I increment this count. Should be always 0 for normal operation.
3. A waveform of the I/O of this module is at usb rx rxda wave of I/O.
4. Bit extract is indicated by the FF output bit_eq. The FF input equation is:at bit extract.Bit extarct is asserted when USB transmission starts and ends when SIE is detected.
5. To identify USB full speed SYNC (0x80), I use shift register of three bits, sync_sfq. It is cleared, while bit extract is de-asserted. Every valid bit is shifted in. The SYNC bits are counted in sync_cnq, till SYNC state is reached.
6. After explaining bit extarct and SYNC count and shift, it is possible to describe the SYNC state machine : usb rx rxda sync state machine..
7. The data path is described at: RX Data Path..
8. The output of the rxda goes to rx_fsm, which is described at: USB RX FSM..

Contact me now at:

I would be happy to offer my services. Call ASAP !

Home

CPU 8051 main features

synthesize flow usb full speed final project - invitation