ASIC/FPGA Design and Verification Out Source Services

The following is my first example with systemc verification package..

1. The code is first written in code style of the SCV examples. It is a standalone program, which can be run. Results are printed for visual inspection.
2. The make file is the same as in the SCV examples.


3. The project requirements are as follows:
4. The DUT checks an input stream. If there two or less zeros, an AIS state is declared.
5. When in AIS state, the input stream is checked and if there are more than 6 zero bits in 1024 bits, the AIS state is exit.
6. The input interface is byte wide with data valid.
7. The verification environment generates transactions. Each transaction is 512 bits wide.
8. The user (verification engineer) can select how many zero bits to generate in each transaction.
9. The generator also generates 10 locations in random.
10. The location will be used for zero bits generation.
11. The code is available at download area: look for scv_ais_gen.tar.gz
    It can also be loaded directly from: code

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