ASIC/FPGA Design and Verification Out Source Services

1. The monitor is easily attached to an AHB interface.


2. The monitor does not replace a conventional debug with waves procedure.


3. Sometimes simulation are very long, which makes it impossible to record waves for the entire simulation. The monitor helps you locate those areas, which need debug and waves.


4. The output log looks like:"Log Example".


5. The code for the monitor and its instantiation can be found in the download area( look for AHB monitor string ).


6. Some tips for debugging an AMBA based SOC designs.
   



7. If you liked this AHB monitor, you might also be interested in this I2C monitor. The I2C monitor is part of self study project of a verification environment, which uses memories (read only from the verilog test-bench) and VPI (c code) to drive and monitor data to/from DUT,



8. Also avialable on this site (non free): An AHB VHDL project, built of two AHB masters, one arbiter, one AHB to APB bridge and one simple APB slave. If you are interested in this project as a graduate project, contact me via mail and put in the subject: non free AHB project.

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SD slave with Samsung flash (k9f1208) (vhdl project). ARM code to readmemhex verilog simulation format usage of queues in C++ and discusses some motivation to implement it in verification environments

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