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I2C master connected and tested with LEON Processor

Introduction:
This design uses the open core's I2C master. The core's CPU interface is modified from WISHBONE to AMBA/APB. The latter is done in order to test the core and its new APB interface with LEON processor . LEON is written in VHDL therefor the core's VHDL RTL design is tested. The core also contains a test bench and simulation model for I2C slave, written in VERILOG. From the VERILOG test bench only the initialization procedure is taken and the I2C slave model is translated to VHDL. Main Features of This Design and Its Verification.
This I2C, with APB, is also available in this site in a verilog code: An I2C verification environment, which uses memories and VPI (c code) to drive and monitor data to/from verilog RTL.

I2C with APB CPU interface

I2C model for simulation written in VHDL

List of files, which need to be modified in LEON, to add an APB slave

Assembly code for LEON processor, which initialize and operate the I2C core

Simulation stop and control from LEON CPU.

Compilation script for LEON + I2C RTL design and simulation slave for GHDL (free VHDL simulator).

LEON script DRAM model (MICRON) modified to be able to be compiled on GHDL.

VHDL component to generate VCD waves to replace GHDL VCD wave dump option.The latter, when enabled dumps signals for the entire design, which strongly impacts simulation performance and disk space usage.At bottom of the page this is explained in detail (probe_i2c_slv.vhd).

For more information send mail with subject LEON_I2C.

I2C with APB CPU interface

The core RTL consists three files. The CPU interface is in the top. So only

this file has been modified. The modification are at the file:

pini_i2c/i2c_master_top.vhd. The file can be accesses from the download link.

I2C model for simulation written in VHDL

The translation is in pini_i2c/pk_i2c_slave_model.vhd. In addition to the translation a few modification to the code were required:
1. Join to one VHDL process the assorted always blocks which drive the same
signal:
always @ ...
A <= condition 1
always @ ...
A <= condition 2
...
process(...
A <= '1' when condition 1 else ....
A <= condition 1
2. I needed to add a new state for I2C read, namely:
constant data_ack_rd : std_logic_vector(2 downto 0) := "110";--Pini read bug fix
This is best explained in the code:
--Pini add a new state for read. At this point a decision has to be
--taken if continue to drive data, during I2C master read, or stop.
--As opposed to the current design, we don't have the info to decide
--on this clock. On the next clock we look on the acknowledge and
--decide.

List of files, which need to be modified in LEON, to add an APB slave

./leon/mcore.vhd

./leon/leon_eth_pci.vhd

./leon/iface.vhd

./leon/leon_eth.vhd

./leon/leon.vhd

./leon/apbmst.vhd

./leon/leon_pci.vhd

./pini_i2c/i2c_master_byte_ctrl.vhd

./pini_i2c/i2c_master_top.vhd

./tbench/fmf/tbgen.vhd

./tbench/tbgen.vhd

./tbench/leonlib.vhd

Assembly code for LEON processor, which initialize and operate the I2C core
The code is based on supplied LEON boot program. The I2C modifications start:
!Pini
100:
!leon config reg read
set 0x80000024, %g1
ld [%g1+0], %g2
nop
!Pini apb I2C check 0x0E0..0x0FC
!PRER_LO load prescaler lo-byte
set 0x800000E0, %g1
The file is accessible via the download link of this site.

Simulation stop and control from CPU.

The LEON processor in test read expected registers and compare the results with known values. Should it read erred data, it has the means to stop the simulation via the monitor (mon.vhd). In this case a write to address 0x8ffffffc stops the simulation.

When an error is detected branch forward to label 101 is done. Registers %g1 and %g2 contain the error code. The value 0 on %g1 is reserved to test end with no errors.

mov 0x00000000, %g1 !program ended okay without errors
101:
nop
!Pini Stop simualtion. While stop loop forever.
set 0x8ffffff8, %g3
st %g1, [%g3]
nop
nop
nop
st %g2, [%g3+4]
ba 101b
nop

Compilation script for LEON + I2C RTL design and simulation slave for GHDL

First I modified the script which came with LEON package to find the files and compilation order automatically. This is because I had problems on linux. The GHDL windows version works fine with the supplied script.

The main important part of the script is therefor the first line:

nice --adjustment=5 ghdl -i --workdir=leon/work --ieee=synopsys pcisim/*.vhd pini_i2c/*.vhd pini_mon/mon.vhd pini_mon/probe.vhd pini_mon/probe_i2c_slv.vhd leon/*.vhd tbench/*.vhd

LEON script DRAM model (MICRON) modified to be able to be compiled on GHDL

When I tried to simulate LEON on linux it failed, with GHDL version 0.26. On the windows version 0.25, it worked fine. After checking with GDB, I managed to find what is currently upsetting the GHDL in the MICRON DRAM model.
This was this statement:
WAIT ON Sys_clk, RAS_clk;
which was replaced by:
IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN
I also added these signals to the sensitivity list.
PROCESS(Sys_clk, RAS_clk)

VHDL component to generate VCD waves to replace GHDL VCD wave dump option:

GHDL has a very restricted capability when it comes to generating VCD waves. It either produces VCD for the entire design for all simulation time. This yields a very big file, which is not easy to handle. This project mili-seconds of simulation. To overcome bulky VCD files, I generate my own form the VHDL code (example: probe_i2c_slv.vhd). This way it is easy to select what signals to dump and on what time.

To save time, the VHDL creates a list file in the easiest format. A PERL script (wave_simili.pl) comes later to convert it a format, which some free-ware translates it to VCD (Lst2vcd.c).