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Replacing the asynchronous SRAM with a synchronous write memory.

1. The asynchronous RAM was probably the only choice available on the evaluation board, when the design was first done.


2. Today synchronous memories are common and good practice.


3. I selected a memory with synchronous write and asynchronous read. This model is very popular with FPGA memories.


4. Usually the read data output is sampled. This is what I did. The data is sampled when the read RAM strobe is asserted.


5. The code is now more synthesis friendly as former asynchronous memory implementation used some logic on the clock to generate a write pulse.


6. To go back to the VHDL IP main page: main .
   

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