ASIC/FPGA Design and Verification Out Source Services

VHDL IP Stack

model for synchronous write memory.

1. The main page of this project: implementation of a lower layers of a standard TCP/IP stack based on a free code from University of Queensland.



2. The memory write operation is synchronous and when the write strobe is asserted the data on data in is stored to the address location on the rising edge of the clock. The read is available after, an optional propagation delay, on the output as a function of input address lines.





MEMORY/sync_mem.vhd

    1 -------------------------------------------------------------------------------
    2 -- memory.vhd
    3 --
    4 -- Author(s):     Pinhas Krengel http://bknpk.dynu.com/my_web/index.html
    5 -- Created:       Jan 2009
    6 -- Last Modified: Feb 2009
    7 -- 
    8 -- A model describing the static synchronous RAM used on board.
    9 -- positive edge amd wr store data to address location.
   10 -- read data is latched and hold when rd is asserted.
   11 
   12 --http://www.doulos.com/knowhow/vhdl_designers_guide/models/generic_largecapacity_ram_model/
   13 -- +-----------------------------+
   14 -- | Copyright 1992-2008 DOULOS  |
   15 -- |       Library: memory       |
   16 -- |    designer : Tim Pagden    |
   17 -- +-----------------------------+
   18 -------------------------------------------------------------------------------
   19 
   20 
   21 library IEEE;
   22 use IEEE.std_logic_1164.all;
   23 
   24 
   25 use STD.textio.all;
   26 use IEEE.STD_LOGIC_TEXTIO.all;
   27 
   28 entity sync_wr_mem is
   29   port (
   30     ck : in  STD_LOGIC;
   31     rd : in  STD_LOGIC;
   32     wr : in  STD_LOGIC;
   33     di : in  STD_LOGIC_VECTOR ( 7 downto 0);
   34     do : out STD_LOGIC_VECTOR ( 7 downto 0);
   35     ad : in  STD_LOGIC_VECTOR (18 downto 0)
   36   );
   37 end sync_wr_mem;
   38 
   39 architecture sync_wr_mem_arch of sync_wr_mem is
   40 
   41 signal ldatar: STD_LOGIC_VECTOR (15 downto 0);
   42 
   43 begin
   44 
   45   process (ck, ad, rd) --sync write async read
   46   type Item;
   47   type ItemPtr is access Item;
   48   type Item is
   49   record
   50     NextItem: ItemPtr;
   51     Address:  STD_LOGIC_VECTOR (18 downto 0);
   52     Word:     STD_LOGIC_VECTOR ( 7 downto 0);
   53   end record;
   54   variable Head: ItemPtr;
   55 
   56   procedure Get (
   57     Addr: in  STD_LOGIC_VECTOR (18 downto 0);
   58     Word: out STD_LOGIC_VECTOR ( 7 downto 0)
   59   ) is
   60   -- Get the contents of the ram with address = Addr
   61   variable Ptr: ItemPtr;
   62   variable my_line1 : line;
   63   begin
   64     Ptr := Head;
   65         --
   66         write(my_line1, string'("dbg mem rd Addr "));
   67         hwrite(my_line1, '0' & Addr);
   68         writeline(output, my_line1);
   69     while Ptr /= null loop
   70       if Ptr.Address = Addr then
   71         Word := Ptr.Word;
   72                 --
   73             write(my_line1, string'("dbg mem lookup "));
   74             hwrite(my_line1, '0' & Ptr.Address);
   75             write(my_line1, string'(" "));
   76             hwrite(my_line1, Ptr.Word);
   77         write(my_line1, string'(" at "));
   78         write(my_line1, now);
   79             writeline(output, my_line1);
   80         return;
   81       end if;
   82       Ptr := Ptr.NextItem;
   83     end loop;
   84     Word := (others => 'U');
   85   end Get;
   86   procedure Set (
   87     Addr: in  STD_LOGIC_VECTOR (18 downto 0);
   88     Word: in  STD_LOGIC_VECTOR ( 7 downto 0)
   89   ) is
   90   -- Set the contents of the ram with address = Addr to Word
   91   variable Ptr, PreviousPtr: ItemPtr;
   92   variable all_u : STD_LOGIC_VECTOR ( 7 downto 0);
   93   variable my_line1 : line;
   94   begin
   95     all_u := (others => 'U');
   96     Ptr := Head;
   97     PreviousPtr := null;
   98         write(my_line1, string'("dbg mem wr Addr "));
   99         hwrite(my_line1, '0' & Addr);
  100         write(my_line1, string'(" "));
  101         hwrite(my_line1, Word);
  102     write(my_line1, string'(" at "));
  103     write(my_line1, now);
  104         writeline(output, my_line1);
  105     while Ptr /= null loop
  106       if Ptr.Address = Addr then
  107         if Word = all_u then
  108           -- Delete item from list...
  109           if PreviousPtr = null then
  110             Head := Ptr.NextItem;
  111           else
  112             PreviousPtr.NextItem := Ptr.NextItem;
  113           end if;
  114           DEALLOCATE (Ptr);
  115         else
  116           Ptr.Word := Word;
  117         end if;
  118         return;
  119       end if;
  120       PreviousPtr := Ptr;
  121       Ptr := Ptr.NextItem;
  122     end loop;
  123     if Word /= all_u then
  124       -- Insert new item into list...
  125       Ptr := new Item'(NextItem => null, Address => Addr, Word => Word);
  126       if PreviousPtr = null then
  127         Head := Ptr;
  128       else
  129         PreviousPtr.NextItem := Ptr;
  130       end if;
  131     end if;
  132   end Set;
  133 
  134   variable D: STD_LOGIC_VECTOR (7 downto 0);
  135 
  136   begin
  137     Get(ad, D);
  138     do <= D;
  139 
  140     if(ck'event and ck = '1') then
  141       if(wr = '1') then --write
  142         Set (ad, di);
  143       end if;
  144     end if;
  145   end process;
  146 
  147 end sync_wr_mem_arch;
  148 
  149 

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