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Post layout gate-level +SDF simulation

This page explains how to simulate a post layout gate-level + SDF VHDL net-list. GHDL, free VHDL simulator, is used.

1. The net-list and SDF are generated using netgen command:
   netgen -sim -ofmt vhdl test.ncd
   Two files are generated: test.vhd and test.sdf.
   


2. The compilation of SIMPRIM library is tricky. The first two files compile easily:
   ghdl -a --work=simprim --workdir=simprim --ieee=synopsys -fexplicit simprim_Vcomponents.vhd
   ghdl -a --work=simprim --workdir=simprim --ieee=synopsys -fexplicit simprim_Vpackage.vhd
   


3. The library simprim_VITAL.vhd is chopped using some PERL utility, which I found on the WEB:
   xilinx chop 1
   xilinx chop 2
   Chopping the big VITAL library file into many single component in a single file, allows to ignore problematic components, which GHDL can not compile.
   


4. The test-bench and net-list compilation script using the SIMPRIM package looks like:
   #~/bin/bash
   
   rm -f ip_stack_tsb
   ghdl -i --warn-no-vital-generic --workdir=work test.vhd ../PostNGDsim/TB_1/*.vhd ../MEMORY/sync_mem.vhd
   ghdl -m --warn-no-vital-generic --workdir=work -P./simprim --ieee=synopsys -fexplicit ip_stack_TSB
   




5. Last is the run simulation command, which unfortunately fails on a GHDL error.
   ./ip_stack_tsb --stop-time=${Stime}us --assert-level=error --sdf=u_dut=test.sdf --stack-max-size=16384
   Changing the value of the stack does not help.
   
6. ./ip_stack_tsb:internal error: cannot allocate stack: memory exhausted.
   

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