ASIC/FPGA Design and Verification Out Source Services

The following describes the synthesis of the VHDL IP stack, using xilinx XST.

1. The synthesis is done with the free xilinx tool: Release 10.1.03 - xst.


2. The package was installed on a debian linux distribution running on a co-linux system.


3. In order to set the xilinx tool environment, one has to run the following command from xilinx installation location. On my system:
   /home/pini/Home_2/Xilinx/10.1/ISE$
   . settings32.sh
   Assuming a default linux bash shell.
   echo $SHELL
   /bin/bash
   


4. Non synthesis code is needed to be marked out in order to ignore it, during synthesis: For debug purpose, I added some print messages using VHDL text IO library. Also, since GHDL does not print to the VCD wave a type variable like the ones used for state machine code in this project, this debug-code has to be marked out as well.
   This is done using the following statements:
   -- synthesis translate_off
   ...
   -- synthesis translate_on
   


5. The XST requires the following input files, when operated in batch mode.



File name	Description
synt.unx	A bash script to invoke XST.
synt.xst	A text file with all input control parameters for synthesis.
test.prj	A text file listing all VHDL source files including the package.


Note: the BUFG component is not on the synthesis VHDL file source list while it is on the simulation source list. In order not to use the XILINX library at this stage of simulation, I wrote a component for simulation for that purpose. To get the files, go to XST input files.


6. While the XST tool generates many files, I review only the log file, synt.syr. The second important generated file is synt.ngc, which is required to the next step in generating a downloadable bit-stream to the FPGA NGD .


7. The XST log file should be, of course, clean of errors.
   As for warnings, I can only point out those I ignored and those I fixed for this project.


8. This type of warning I ignore
   WARNING:HDLParsers - A logical library name ('../arp3.vhd') may not have the characters '\/.: ': Library name ../arp3.vhd not added to library search list.
   


9. Some of the components have been built for general purposes and therefore some of their inputs or outputs are not used on this particular implementation. The synthesis tool, XST, places a warning message on each unconnected pin, which it finds.
   WARNING:Xst:753 - "/home/pini/Home_2/VHDL_IP_Stack/CODE/XST_synt/../stack3.vhd" line 394: Unconnected output port 'idle' of component 'ARPSnd'.
   WARNING:Xst:1306 - Output > is never assigned.
   Same applies to this kind of warning:... is assigned but never used...
   


10. Some signals can be trimmed and their synthesis warning are ignored:
    WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
    


11. Warnings related to missing signals in a sensitivity list must be fixed. If not fixed, a difference between simulation and real design, after synthesis may exist.
    This happened due to a fix, which I made. Fortunately the XST synthesis tool is " kind enough" to tell what signal is missing and I add it to the sensitivity list.
    




12. One thing to note is device utilization. High utilization may result in longer RTL to bit-stream cycle time.
    
    Device utilization summary:
    ---------------------------
    Selected Device : 4vlx25ff668-10
    Number of Slices: 1451 out of 10752 13%
    Number of Slice Flip Flops: 1447 out of 21504 6%
    Number of 4 input LUTs: 2464 out of 21504 11%
    Number of IOs: 63
    Number of bonded IOBs: 57 out of 448 12%
    Number of GCLKs: 1 out of 32 3%
    

To go back to the VHDL IP main page: main .
To go to next step: NGD .

Contact me now at:

I would be happy to offer my services. Call ASAP !

Home	some memory VHDL models Basic test for open cores 1G eth UDP / IP Stack using, specman for verification Download Area