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The following describes the NGD step of the VHDL IP stack, using xilinx free tool.

1. The synthesis is done with the free xilinx tool: Release 10.1.03 - ngdbuild K.39 (lin)


2. NGD reads in the net-list that XST generated and creates a Xilinx Native Generic Data Base (NGD).


3. In this step a user constraint file (UCF) is required. I'll only constrain timing issues, as I don't have any pin-out specifications.


4. At this step a VHDL net-list is also generated. It is recommended at this stage to run only few tests with the post-synthesis net-list, merely to verify the synthesis process did not fail on basic issues. A more intensive test scheme should be run on gate-level with timing on a post-layout net-list.


5. The NGD outputs a file synt.ngd, which is required for the next step in the flow.


6. The file synt.bld is the report and has to be reviewed in order to see that no errors exist.



To go back to the VHDL IP main page: main .
To go to previous XST step: XST .
To go to next MAP step: MAP .
To go to Post synthesis/NGD simulation using VHDL net-list and GHDL free simulator : post ngd simulation VHDL .
To go to Post synthesis/NGD simulation using verilog net-list and icarus free simulator : post ngd simulation verilog .


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