ASIC/FPGA Design and Verification Out Source Services

VHDL IP Stack

This process is used in the test-bench to optionally print a transmitted packet.

1. 
     --optinal record tx packet to the log file
     process(x_clk)
     variable ls_nibble : bit := '0';
     variable tx_byte : std_logic_vector(7 downto 0);
     variable my_line : line;
     variable tx_byte_cnt : integer := 0;
     begin
       if(enable_record and x_clk'event and x_clk = '1') then
         if(tx_en = '1') then
             if(ls_nibble = '0') then
             tx_byte(3 downto 0) := txdata;
             ls_nibble := '1';
           else
             tx_byte(7 downto 4) := txdata;
             ls_nibble := '0';
   
             write(my_line, string'("TX data "));
             hwrite(my_line, tx_byte);
             write(my_line, string'(" count "));
             write(my_line, tx_byte_cnt);
             write(my_line, string'(" at "));
             write(my_line, now);
             writeline(output, my_line);
   
             tx_byte_cnt := tx_byte_cnt + 1;
           end if;
         end if;
       end if;
     end process;
   


2. To go back to the transmit page: TX .

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