Test Bench Configuration.
First a name is selected for the eVC.
--logical name for the eVC instance.
extend uart_rx_env_name_t : [UART_RX_U];
eVC instantiation and general specman configuration follows:
-- Instantiate the eVC under sys.
extend sys {
uart_rx_evc : UART_RX_U uart_rx_env_u is instance;
setup() is also {
set_config(print,scale,ps);
--Error: Specman run reached the tick_max configuration limit (10000)
set_config(run, tick_max, 100000);
--set_config(run, tick_max, UNDEF);
};
};
Some notes on the configuration:
- Scale is to have time displayed in ps in the log:
[128870000 ps] sys-@0: OBJ All objections to TEST_DONE dropped in sys -
- Without increasing the tick MAX, the simulation fails on the end. It is simply has to be bigger than the drain time, which was defined in the
sequence.
Last is the hdl path declarations:
extend UART_RX_U uart_rx_env_u {
keep hdl_path() == "rx_tb"; --name of the VHDL entity
keep agent.sig.clk_p.hdl_path() == "clk";
keep agent.sig.rst_p.hdl_path() == "reset";
keep agent.sig.ck_en_p.hdl_path() == "ck_en";
keep agent.sig.full_clr_p.hdl_path() == "full_clr";
keep agent.sig.rx_in_p.hdl_path() == "rx_in";
...
To go to main project: main project page
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