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This pages describes the UART TX monitor file.

As opposed with the BFM, the monitor is part of the passive eVC. It is to be used not only in the stand-alone unit level environment, but also in the full-chip verification environment.

The monitor uses a scoreboard for data integrity check. It assumes that data at the DUT output will be available after the input serial data collection is completed.
This is to say that the reference model, based on this scoreboard is simple.
When input data collection ends, an entry is added to the scoreboard . When a data byte at the output is ready, a compare method is called. If compare is okay the scoreboard is updated. If not a DUT error is issued.
Note: when a data out is compared, the scoreboard must not be empty. This is shown in the compare method below:

  1. --data intergrity check
  2. mon_tx_data_cmp(tx_d_byte : byte) is {
  3.   check that !scbd.is_empty() else
  4.   dut_error("tx_mon_u data output without input ", tx_d_byte);
  5.   check that tx_d_byte == scbd[0] else
  6.   dut_error(
  7.     "tx_mon_u data compare error dut=", tx_d_byte,
  8.     " exp=", scbd[0]
  9.   );
  10.   messagef(NONE, "%s tx_mon_u date compare ok of %x", name, tx_d_byte);
  11.   scbd.delete(0);
  12. };--mon_tx_data_cmp

The TCM, which collects data from the output is more complex. As opposed the one in the input, which merely collects bytes, this one as to work out a serial to parallel conversion.
Serial data is stored in a list. After collection of eight bits, unpack to byte is done. The TCM also handles coverage, which is explained in the following page. Note that the TCM starts its main loop after reset negation.

  1. mon_tx_data_tcm() @sig.clk_r_ev is {
  2.   var txd_l : list of bit;
  3.   var last_bit : bit;
  4.   var first_bit : bit;
  5.   
  6.   wait true (sig.rst_p$ == 0);
  7.   message(NONE, "tx_mon_u reset wait ended ", name);
  8.   while(TRUE) {
  9.     --wait for data start bit
  10.     wait true (sig.txd$ == 0);
  11.     for i from 0 to 7 do {
  12.       wait [data_wait_cycles];
  13.       txd_l.add(sig.txd$);
  14.       if(i == 7 && has_coverage) then {
  15.         last_bit=sig.txd$;--last bit for coverage
  16.       } else {
  17.         if(i == 0 && has_coverage) then {
  18.           first_bit=sig.txd$;--first bit for coverage
  19.           start cov_first_bit_after_start(first_bit);
  20.         };
  21.       };
  22.     };--for
  23.     --make sure last bit is stop bit
  24.     wait [data_wait_cycles];
  25.     check that sig.txd$ == 1 else
  26.     dut_error("tx_mon_u end bit not 1 ", sig.txd$);
  27.     if(has_coverage) then {
  28.       start cov_stop_bit_start_tcm();
  29.       start cov_last_bit_before_stop(last_bit);
  30.     };
  31.     
  32.     --end bit was okay - check that the output data is okay too.
  33.     if(data_out_reverse_flg) then {
  34.       txd_l=txd_l.reverse();
  35.     };
  36.     var tx_d_byte : byte;
  37.     unpack(packing.low, txd_l, tx_d_byte);
  38.     message(NONE, "tx_mon_u data\n", name) {
  39.       print txd_l using hex;
  40.       print tx_d_byte using hex;
  41.     };--message
  42.     txd_l.clear();
  43.     mon_tx_data_cmp(tx_d_byte);
  44.   };--while
  45. };--mon_tx_data_tcm

Rate of data transmission may change. This is the case between the unit level TX environment and the combined RX to TX one. The collection is controlled by the switch: data_wait_cycles.
  1. data_wait_cycles : uint;
  2. keep soft data_wait_cycles == 15;

15 is the default and is the value for the unit level.



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