This pages describes the UART TX signal map file.
This file declares all ports that are used in this eVC.
package pk_tx;
unit sig_map_u {
clk_p: in simple_port of bit is instance;
rst_p: in simple_port of bit is instance;
keep bind(clk_p, external);
keep bind(rst_p, external);
event clk_r_ev is rise(clk_p$) @sim;
txd: in simple_port of bit is instance;
...
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