VHDL test bench
This is a VHDL test bench, which instantiate DUT and code, that is required by specman. The specman code is show below:
ARCHITECTURE behavior OF tx_tb IS
--specman
component comspec
end component;
for all: comspec use entity work.SPECMAN_REFERENCE (arch);
To go to main project: main project page
|
Search This Site
Feedback This Site
new pages on this site