Simulation of the open cores 1G eth UDP / IP Stack using,
the free VHDL simulator: ghdl.

1. In search for self study projects for this site, I have downloaded from the open cores site, this UDP project. This project was also simulated with cpp packet generator.


2. In this site, I use ghdl free simulator in many cases. The ghdl script for this project is a bit more complex. As opposed to the script used at UART, the compilation command is different, because this project uses a few VHDL packages.
   


3. The script accepts a few parameters:
   
   1. #clear   - removes the compilation directory before start
      
   2. #no_comp - skips compilation
      
   3. #vcd     - run with vcd
      
   4. #200     - run 200 us. This is an optionally parameter. Default is 100 us.
      
   
   


4. VHDL packages are best handled automatically by the ghdl tool using a two step compilation scheme:
   
   
   1. ghdl -i --workdir=work --ieee=synopsys UDP_complete_nomac_tb.vhd ../../rtl/vhdl/*.vhd >& cmp.log
      
   2. grep vhd cmp.log > /dev/null
      
   3. if [ $? -eq 0 ] ; then
      
   4.   echo "compilation failed"
      
   5.   cat cmp.log
      
   6.   exit 1
      
   7. else
      
   8.   ghdl -m --workdir=work --ieee=synopsys UDP_complete_nomac_tb
      
   9. fi
      
   
   


5. I have placed the ghdl script in the test bench location:
   udp_ip_stack/trunk/bench/vhdl
   
   



6. The version of code, which I downloaded, with the ghdl script, simulation log and waves in VCD format can be downloaded from:
   udp code .
   


7. This VHDL DUT will be used to develop a self study verification project. The verification will generate ARP or UDP packets, drive the packets to the DUT and check the DUT output.
   The first step in creation this eVC verification project, is to design a UDP IP sequence item. Some consideration in designing the sequence item are explained at: link .
   


8. An initial version of the code, not fully compiled and tested, can downloaded from: code .
   


9. This open core DUT and its test-bench was also compiled, using cadence ncvhdl tool. Please see the following: link. .
   

Home	IP TTL filter: digital design, implemented in VHDL SD slave with Samsung flash (k9f1208) (vhdl project).