ASIC/FPGA Design and Verification Out Source Services
This tip shows a simple synchronization between two clock domains, using specman.
In this case I needed to force a DUT signal to a value very close to overflow and do the same in the environment. The force, to the DUT, was done with one clock while the environment works with another clock, the one used for the CPU interface.
So I had to capture the force data value, which was communicated via a method port, and synchronize it to the CPU clock.
First I captured the data, arriving via the method port and set a flag.
Second I re-set a flag and use the data, with the other clock.
uart_counter_froce_mp : in method_port of uart_counter_froce_t is instance;
keep bind (uart_counter_froce_mp, empty);
counter_force_flg : bool;
keep soft counter_force_flg == FALSE;
counter_force : uint;
keep soft counter_force == 0;
counter : uint;
keep soft counter == 0;
uart_counter_froce_mp(vf : uint) is {
counter_force = vf;
counter_force_flg=TRUE;
};--uart_counter_froce_mp
uart_force_tcm() @sigmap.clk_r is {
while(TRUE) {
wait true (counter_force_flg == TRUE);
wait delay(1 ps);
counter_force_flg=FALSE;
counter=counter_force;
};--while
};
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