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Specman: how code style affects performance

1. A friend of mine, Avidan Efody , called me to review his code for some double triggering event. When I looked on his code, I said that his style could be improved in order to increase performance.
2. My argument was that the more specman is called the less speed is reached as there is more task switching, between the engine of the VERILOG and specman.
3. My friend's code include a VERILOG always style coding as shown below:
     kuku : uint;
     keep soft kuku == 0;
     always_kind_tcm() @ clk$ is {
       while(TRUE) {
         if(cnt$ == 10) then {
           kuku+=1;
         };
         wait cycle;
       };
     };
   
4. My code was based on emitting an event only on a specified value of the counter:
     event cnt_10_ev is true(cnt$ == 10) @ clk$;
     cnt_10_event_tcm() @ cnt_10_ev is {
       while(TRUE) {
         kuku+=1;
         wait cycle;
       };
     };
   
5. A better code style yields in a much better performance.
   unit env_u {
     clk : in event_port is instance;
     keep bind(clk, external);
   
     cnt : in simple_port of uint (bits:16) is instance;
     keep bind(cnt, external);
   
     !cnt_10s : uint;
   
     event every_10_clks_e is true(cnt$ == 10) @ clk$;
   
     on every_10_clks_e {
       cnt_10s+=1;
     };
   };
   
6. The results are: (ordered as good , better and best)
   simulator 10.33% specman 89.67%
   simulator 13.48% specman 86.52%
   simulator 20.11% specman 79.89%


The pro-filer was invoked initially from the code and later moved to the script.
extend sys {
  ...
  setup() is also {
    set_config(run, tick_max, MAX_INT, exit_on, error);
  --specman("set profile");
  };
};

or from the command line:
specrun -p "load external_bind_empty; test; set profile" ncsim .....


8. The entire package can be downloaded from: specman performance test code
   It includes the VERILOG test-bench, specman e-code, script to compile and run + specman profiler results. The design was used on NCSIM simulator.


9. The following commands were used to compile and simulate the design:
   
   
   
   #!/bin/bash
   
   specman -command "load external_bind_empty.e ;write stubs -verilog specman.v"
   ncvlog top.v specman.v;
   ncelab specman specman_wave top -access +rw -snapshot avidan
   #specrun -p "load external_bind_empty; test" ncsim -NBASYNC -gui avidan
   specrun -p "load external_bind_empty; test; set profile" ncsim -NBASYNC -batch avidan
   
   

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