ASIC/FPGA Design and Verification Out Source Services
This tip suggest a way to debug coverage.
I have written some cover items, using specman, when it did not work, I first wanted to make sure that all events are emitted.
To debug it, I added a few statements in my TCL file:
sn collect events fast_uart_sig_cov_u.*_ev
run 10 us
sn sh events
sn sh cover fast_uart_sig_cov_u
So I collected some events of interest, only for small time of simulation run time, displayed them, using show event specman command. This was in specman.elog:
--------------------------------------------------
-> 2353000 ps fast_uart_sig_cov_u-@18644.xoff_in_rise_ev step_cnt=0
-> 2353000 ps fast_uart_sig_cov_u-@18644.empty_rise_ev step_cnt=0
-> 3874000 ps fast_uart_sig_cov_u-@18644.xoff_in_fall_ev step_cnt=0
-> 4123000 ps fast_uart_sig_cov_u-@18644.empty_fall_ev step_cnt=0
-> 4147000 ps fast_uart_sig_cov_u-@18644.empty_rise_ev step_cnt=3
-> 4153000 ps fast_uart_sig_cov_u-@18644.empty_fall_ev step_cnt=1
...
This report was created by the command:
sn sh cover fast_uart_sig_cov_u
In this case I wanted to debug a small part of the coverage and text report is okay.
Specman Coverage report
=======================
Command: show cover -kind = full fast_uart_sig_cov_u.*.*
Grading_formula: linear
At least multiplier: 1
Show mode: both
Number of tests: 1
Note: %t is a percent from total, %p is a percent from parent
Cover group: fast_uart_sig_cov_u.xoff_in_fall_ev
==================================================
Grade: 0.75 Weight: 1
** step_cnt **
Samples: 19 Tests: 1 Grade: 0.75 Weight: 1
grade goal samples tests %t step_cnt
------------------------------------------------
1.00 1 1 1 5 0
0.00 1 0 0 0 1
1.00 1 9 1 47 2
1.00 1 9 1 47 3
...
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