ASIC/FPGA Design and Verification Out Source Services

Run a perl script from vim on a specified text block and convert verilog registers and wires to VHDL signals.

  1. In this site I have many examples of running a perl script on block of text from within vim.

  2. This page is yet another example, which I used to translate a design written in verilog to VHDL.

  3. In such cases I create small script per each task. In this case the script is used to convert registers and wires to signals syntax.

  4. To invoke the script just mark its borders (with tags) and run the script:
    'a,'b !perl reg_wire_to_signal.pl

  5. The script is shown below:

    1. #!/bin/perl

    3. while (<STDIN>) {
    4.    chomp($_);
    5.    $flg=0;
    6.    if($_ =~ /reg/) {$flg=1;}
    7.    elsif($_ =~ /wire/) {$flg=1;}
    8.    if($flg == 1) {
    9.       $rangeh="";
    10.       $rangel="";
    11.       if($_ =~ /.*\[([ 0-9]*):([ 0-9]*)/) {
    12.          $rangeh=$1; $rangel=$2;
    13.       }
    14.       @a=split(/--/, $_);
    15.       $a[0] =~ s/ *;/;/;
    16.       $sig_name="";
    17.       if($a[0] =~ /.* ([a-zA-Z_0-9]*) *;/) {
    18.          $sig_name=$1;
    19.          while( length($sig_name) < 12) {$sig_name=$sig_name . " ";}
    20.       }
    21.       $comment="";
    22.       if($_ =~ /.*(--.*)/) {
    23.          $comment=$1;
    24.       }
    25.       print(" signal $sig_name : ");
    26.       if($rangeh ne "") {
    27.          print("std_logic_vector($rangeh downto $rangel);");
    28.       } else {
    29.          print("std_logic;");
    30.       }
    31.       print("$comment\n");
    32.    }
    33.    else {
    34.       if($_ =~ /integer *([a-zA-Z_]*)/) {
    35.          print(" signal $1 : integer;\n");
    36.       } else {
    37.          print("$_\n");
    38.       }
    39.    }
    40. }#while


  6. Similar script, which works on a block of VHDL input and outputs, and converts it to verilog IO syntax, can be downloaded from here.
    The script was extended to also be able to convert VHDL signals to verilog equivalence ( without checking if a reg or wire should be used).
    As usual to fire-up the script, you need to mark up a text block, for instance mark a and b and then type:
    'a,'b !perl vim_vhd_io_to_verilog_io.pl

 


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