ASIC/FPGA Design and Verification Out Source Services

Simulation Control from CPU in SOC.

To simplify verification on SOC, it is sometimes possible to take advantage on an on chip CPU. First the CPU has to be tested anyways. While both VHDL and VERILOG or SPECMAN have strong capabilities to reduce code development, it is much easier to use CPU to control and check result of a simulation. For instance an end of reception may leave a signature in CPU memory. The CPU can than easily read and verify it. A transmission can be captured and if results are good, a flag can be read by CPU general purpose I/O. For CPU, which uses AMBA like ARM and LEON, I have created a monitor. The monitor records to the simulation log the activity on the bus :read and write transactions. It can be set to stop the simulation on detecting a transaction to spare address. The value written to this location may signify test pass (say code 0) or failure (any number > 0). The VHDL monitor is available at the download area:(Look for the name: file the monitor:mon.vhd).

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