ASIC/FPGA Design and Verification Out Source Services

LEON-2 generic testbench (leon2-1.0.32-xst)
Bug reports to Jiri Gaisler, jiri@gaisler.com
Testbench configuration:
32 kbyte 32-bit rom, 0-ws
2x128 kbyte 32-bit ram, 2x64 Mbyte SDRAM
Pini PCIEN
Pini nETHEN
Pini SDRAMEN
PCI: configuration wait 1 ns 00000004
PCI: configuration wait end 105 ns
simulation starts here
PCI: configuration wait 136 ns 00000008
PCI: configuration wait end 375 ns
PCI: configuration wait 406 ns 00000028
P HMASTER_q 0 last HTRANS 10 HADDR_q 00000000 HRDATA 81D82000 at 710 ns
P HMASTER_q 0 last HTRANS 10 HADDR_q 00000004 HRDATA 03000004 at 1110 ns
P HMASTER_q 0 last HTRANS 10 HADDR_q 00000008 HRDATA 821060C0 at 1510 ns
PCI: configuration wait end 1605 ns
PCI: Configuration write 0x00020010 0x7FE00000
PCI: configuration wait 1816 ns 00000008
P HMASTER_q 0 last HTRANS 10 HADDR_q 0000000C HRDATA 81884000 at 1910 ns
PCI: configuration wait end 2055 ns

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