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Reset signal

(i am currently working with a Xilinx FPGA)

1. assuming a Reset signal needed to get to all the design ( User Global reset)
should i insert this signal into a BUFG (Xilinx Silicon Global Buffer line) line like i do with a Clock signal ?
2. is there another way of driving the reset signal through all the design without causing timing violations ?
3. i am aware of the reset modules that makes a "fully" (rise and fall) asynchronous reset to a rising asynchronous and falling synchronously to current clock domain (by double flopping). but what if some registers need to be reset not only with one reset signal but with 3 for example (having OR between them). what is the best way of implementing this?

thanks ahead,
I would certainly recommend using a BUFG. Also note that sometimes not all
FF need to be reset at same time. For control part it is usually the case. For
data path, however, you can have their reset released a clock later, by
adding FF, you can reduce the load on the reset signal.
So this answers both your two first questions: use BUFG and have a seperated
reset for the data path , if possible.
As for your last question, you need to supply more details. My reset signals
are usually simple with no logic at all.

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