ASIC/FPGA Design and Verification Out Source Services

compile the specman code and the VHDL DUT

1. The following pages describe how to compile, elaborate, simulate and debug a specman code using a VHDL DUT and test-bench code. The verification code is part of main project.


2. The design can be compiled and run using the script run_spc.unx. All files can be downloaded from files


3. Note: when the VHDL code changes all commands in the script have to be run. If only the e, specman, code is changed, only the last line is required. This is shown at: run_script_stages


4. First the specman code is compiled. Than a specman stub is created. Note that you need to specify which simulator is used. In my case it is NCVHDL.


5. Instantiating the stub in the VHDL test bench is done in the file pk_tb.vhd. Under the architecture one has to define the specman component:
   --specman
   component comspec
   end component;
   for all: comspec use entity work.SPECMAN_REFERENCE (arch);
   I: comspec;
   and than later:
   --specman
   I: comspec;
   


6. The entity and architecture have to be specified in the NCELAB command. I also name the snapshot.


7. Last is the run command. I prefer batch but one can remove it and use the -gui option.


8. If no input is given in batch the simulation is run. I prefer to control the simulation from a TCL file: tcl

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Also available on this project:

Home	Download Area Extension of the systemc example from cadance of producer consumer.