ASIC/FPGA Design and Verification Out Source Services

VHDL IP Stack

SRAM model for AS7C4096.

1. The VHDL IP stack project uses an on-board external to the FPGA SRAM. Therefor I needed to create a VHDL behavioral model for that memory device.


2. I decided to use a sparse memory model to reduce memory consumption. The idea is that a memory of large address (18 bits) of 16 bits data word consumes, only that much that is written, to the memory model, during simulation.


3. I searched in the internet for such VHDL models and came across a good one from: doulos memory .


4. I took from that code the read and write logic, skipped the diagnose code and modified to my needs. Actually to my SRAM truth table:
   --CE WE OE Data Mode
   --H X X High Z Standby (ISB, ISB1)
   --L H H High Z Output disable (ICC)
   --L H L DOUT Read (ICC)
   --L L X DIN Write (ICC)
   


5. The VHDL code follows. Note that I needed to stop driving the data bus when output enable is de-asserted to avoid contention on the bus.
   
   -------------------------------------------------------------------------------
   -- memory.vhd
   --
   -- Author(s): Pinhas Krengel http://bknpk.dynu.com/my_web/index.html
   -- Created: Jan 2009
   -- Last Modified: Feb 2009
   --
   -- A model describing the static RAM used on board.
   
   --CE WE OE Data Mode
   --H X X High Z Standby (ISB, ISB1)
   --L H H High Z Output disable (ICC)
   --L H L DOUT Read (ICC)
   --L L X DIN Write (ICC)
   -- +-----------------------------+
   -- | Copyright 1992-2008 DOULOS |
   -- | Library: memory |
   -- | designer : Tim Pagden |
   -- +-----------------------------+
   -------------------------------------------------------------------------------
   
   
   library IEEE;
   use IEEE.std_logic_1164.all;
   
   
   use STD.textio.all;
   use IEEE.STD_LOGIC_TEXTIO.all;
   
   entity memory is
     port (
       lcen : in STD_LOGIC; -- chip enable to the left bank of RAM
       loen : in STD_LOGIC; -- output enable to the left bank of RAM
       lwen : in STD_LOGIC; -- write enable to the left bank of RAM
       ldata: inout STD_LOGIC_VECTOR (15 downto 0);-- data lines from the left bank of RAM
       laddr: in STD_LOGIC_VECTOR (18 downto 0) -- address lines from the left bank of RAM
     );
   end memory;
   
   architecture memory_arch of memory is
   
   begin
     
     process (lcen, loen, lwen, laddr)
     type Item;
     type ItemPtr is access Item;
     type Item is
     record
       NextItem: ItemPtr;
       Address: STD_LOGIC_VECTOR (18 downto 0);
       Word: STD_LOGIC_VECTOR (15 downto 0);
     end record;
     variable Head: ItemPtr;
   
     procedure Get (
       Addr: in STD_LOGIC_VECTOR (18 downto 0);
       Word: out STD_LOGIC_VECTOR (15 downto 0)
     ) is
     -- Get the contents of the ram with address = Addr
     variable Ptr: ItemPtr;
     begin
       Ptr := Head;
       while Ptr /= null loop
        if Ptr.Address = Addr then
        Word := Ptr.Word;
        return;
        end if;
        Ptr := Ptr.NextItem;
       end loop;
       Word := (others => 'U');
     end Get;
     procedure Set (
       Addr: in STD_LOGIC_VECTOR (18 downto 0);
       Word: in STD_LOGIC_VECTOR (15 downto 0)
     ) is
     -- Set the contents of the ram with address = Addr to Word
     variable Ptr, PreviousPtr: ItemPtr;
     variable all_u : STD_LOGIC_VECTOR (15 downto 0);
     begin
       all_u := (others => 'U');
       Ptr := Head;
       PreviousPtr := null;
       while Ptr /= null loop
        if Ptr.Address = Addr then
        if Word = all_u then
        -- Delete item from list...
        if PreviousPtr = null then
        Head := Ptr.NextItem;
        else
        PreviousPtr.NextItem := Ptr.NextItem;
        end if;
        DEALLOCATE (Ptr);
        else
        Ptr.Word := Word;
        end if;
        return;
        end if;
        PreviousPtr := Ptr;
        Ptr := Ptr.NextItem;
       end loop;
       if Word /= all_u then
        -- Insert new item into list...
        Ptr := new Item'(NextItem => null, Address => Addr, Word => Word);
        if PreviousPtr = null then
        Head := Ptr;
        else
        PreviousPtr.NextItem := Ptr;
        end if;
       end if;
     end Set;
     
     variable D: STD_LOGIC_VECTOR (15 downto 0);
     
     
     variable my_line : line;
     begin
       if(lcen = '0' and lwen = '1' and loen ='0') then --read
        Get(laddr, D);
        ldata <= D;
   
       write(my_line, string'("dbg ram rda="));
       hwrite(my_line, '0' & laddr);
       write(my_line, string'(" rdd="));
       hwrite(my_line, ldata);
       write(my_line, string'(" at "));
       write(my_line, now);
       writeline(output, my_line);
       end if;
   
     --stop driving the data
     if loen'EVENT and loen = '1' then
        ldata <= (others => 'Z');
     end if;
   
       if lwen'EVENT and lwen = '1' then
        if(lcen = '0') then --write
         write(my_line, string'("dbg ram wra="));
         hwrite(my_line, '0' & laddr);
         write(my_line, string'(" wrd="));
         hwrite(my_line, ldata);
         write(my_line, string'(" at "));
         write(my_line, now);
         writeline(output, my_line);
   
        Set (laddr, ldata);
        end if;
       end if;
     end process;
   
   end memory_arch;
   

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