ASIC/FPGA Design and Verification Out Source Services

VPI memory model

compilation script for icarus.

1. The following simple script is used to compile the assorted files (verilog and c).
   The commands are:
   c compile followed by verilog compile followed by simulation run. If any command fails, the script exits.
   
   #!/bin/bash
   
   rm $1.vvp *.vcd
   iverilog-vpi $1.c || exit
   iverilog -o$1.vvp tb_1.v $1.v || exit
   vvp -M. -m$1 $1.vvp || exit
   


2. To go to the main page of this project: main

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A reference model in systemc using queues, from C++ STD.