ASIC/FPGA Design and Verification Out Source Services

VPI memory model

model for synchronous write memory.

1. I decided to use a sparse memory model to reduce memory consumption. The idea is that a memory of large address (18 bits) using a 16 bits data word, consumes only that much that is written, to the memory model, during simulation.


2. In VHDL, capabilities such as mentioned above, are built in the language. For VERILOG one needs VPI. Simply write it in C.


3. The memory is implemented as a system task. It receives address and data inputs, read and write strobes and it drives data on read.


4. The system task is called from a simple memory model: it samples on positive clock the write inputs and drives the data output on read.


5. The memory is the Design Under Test. It is checked in a small test-bench. The design is compiled using the free VERILOG simulator: icarus.


6. The algorithm is explained in the following page: algorithm


7. The code is described in the following page: code description


8. The compilation script, using the free verilog simulator icarus is described in this page.



9. The VERILOG files: test-bench and DUT as well as the c-code and the compilation script are available at: code


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