ASIC/FPGA Design and Verification Out Source Services
The following describes the MAP step of the VHDL IP stack, using xilinx free tool.
- The PAR program maps the design to a Xilinx FPGA.
- The following command is used:
map -p xc4vlx25ff668-10 -timing -ol high -cm area -pr b -k 4 -c 100 -tx off -o test_map.ncd synt.ngd
- Next I review the map report.
- Note that the number of flip-flop devices is pretty much the same as reported by the synthesis report:
Number of Slice Flip Flops: 1,441
IOB Flip Flops: 7
To go back to the VHDL IP main page: main .
To go to first XST step: XST .
To go to next Palce And Route step: PAR .
Contact me now at: |