ASIC/FPGA Design and Verification Out Source Services

The following describes the MAP step of the VHDL IP stack, using xilinx free tool.

1. The PAR program maps the design to a Xilinx FPGA.


2. The following command is used:
   map -p xc4vlx25ff668-10 -timing -ol high -cm area -pr b -k 4 -c 100 -tx off -o test_map.ncd synt.ngd
   


3. Next I review the map report.


4. Note that the number of flip-flop devices is pretty much the same as reported by the synthesis report:
   Number of Slice Flip Flops: 1,441
   IOB Flip Flops: 7
   

To go back to the VHDL IP main page: main .
To go to first XST step: XST .
To go to next Palce And Route step: PAR .

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