ASIC/FPGA Design and Verification Out Source Services

The following describes the PAR step of the VHDL IP stack, using xilinx free tool.

1. The PAR program palces and routes a design to a Xilinx FPGA.


2. The following command is used:
   par -w -ol high -t 1 test_map.ncd test.ncd
   


3. Next I check that there are no logical and timing errors.


4. For this project timing constraints were defined in the UCF file.


5. In this case some of the constraints were not satisfied.
   -------------------------------------------------------------------------------------
   * TSF2P = MAXDELAY FROM TIMEGRP "FFS" TO TIMEGRP "PADS" 10 ns | MAXDELAY| -3.712ns| 13.712ns| 29| 78908
   -------------------------------------------------------------------------------------
   


6. Fortunately there was some spare and the FF to PAD is now increased to 15.


7. Last we need to generate a net-list and timing annotation - SDF. The command is:
   netgen -sim -ofmt vhdl test.ncd
   Two files are created: test.sdf and test.vhd.
   



To go back to the VHDL IP main page: main .
To go to first XST step: XST .
To go to post layout gate-level + SDF VHDL net-list simulation: GL sim .

I would be happy to offer my services. Call ASAP !

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