ASIC/FPGA Design and Verification Out Source Services

Post synthesis/NGD simulation

This page explains how to simulate a post NGD verilog net-list.

1. Post NGD net-list uses UNISIM library. The net-list is generated using the following command:
   netgen -sim -ofmt verilog synt.ngc
   


2. The compilation script compiles both the test-bench and DUT net-list verilog files. The memory model is written in c, using VPI so the script also compiles the c-code. The script is given a path where to look for UNISIM components (-y /home/pini/Home_2/Xilinx/10.1...).


3. After the simulation ends, there are a few topics to consider: visual inspection of VCD waves, compare transmit data of the current post synthesis (NGD) simulation with the one of the RTL and CPU run time. CPU run time, in this case, is done in comparison to GHDL run on post NGD net-list. Since the VHDL and VERILOG simulation are both carried on the very same computer, it gives us a good view on on each simulator performance using the two major free simulators (GHDL versus icarus).


4. The performance is measured using linux time command. co-linux is used under windows XP.


5. The design contains 1447 flip-flops.
   The design is simulated for 1199700 ns.
   All signals are recorded using VCD format.
   

   VERILOG	VHDL
   real    0m55.051s	1m24.521s
   user    0m53.170s	1m23.810s
   sys     0m1.100s	0m0.530s





6. The code can be downloaded following this link: code

To go back to the main page: VHDL IP top
To go to post layout gate-level + SDF simulation page: post PAR sim

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