This pages describes the UART TX monitor file.
As opposed with the BFM, the monitor is part of the passive eVC. It is to be used not only in the stand-alone unit level environment, but also in the full-chip verification environment.
The monitor uses a scoreboard for data integrity check. The input serial data may arrive to scoreboard later than the collected output,
as opposed to the monitor of the
TX.
So both the input collect data TCM and the output one store data in the scoreboard and than call to the compare method. If the absolute difference between input and output lists is greater than one, an error is issued. If both lists are not empty a compare is done.
mon_rx_data_cmp() is {
--The output data may come before the input data.
var szi : int = scbd_inp.size();
var szo : int = scbd_out.size();
check that abs(szi - szo) <= 1 else dut_error(
"scbd size error i=", szi, " o=", szo
);
if(szi != 0 && szo != 0) then {
check that scbd_out[0] == scbd_inp[0] else
dut_error(
"rx_mon_u data compare error dut=", scbd_out[0],
" exp=", scbd_inp[0]
);
messagef(NONE, "%s rx_mon_u date compare ok of %x", name, scbd_out[0]);
scbd_inp.delete(0);
scbd_out.delete(0);
};
};--mon_rx_data_cmp
The RX DUT has a FIFO clear input. Optionally it can be set to remove the output full indication.
fifo_clr_tcm() @sig.clk_r_ev is {
var del : byte;
gen del keeping {it >= 0 && it <= 3;};
wait [del] * cycle;
sig.full_clr_p$=1;
wait [1] * cycle;
sig.full_clr_p$=0;
};--fifo_clr_tcm
RX data is collected, when DUT sets its output full.
mon_rx_data_out_tcm() @sig.clk_r_ev is {
wait true (sig.rst_p$ == 0);
message(NONE, "mon_rx_out_tcm reset wait ended ", name);
while(TRUE) {
wait true (sig.full_p$ == 1);
wait [1] * cycle;
messagef(NONE, "%s mon_rx_out_tcm d_out %02x", name, sig.d_out_p$);
scbd_out.add(sig.d_out_p$);
mon_rx_data_cmp();
start fifo_clr_tcm();
wait true (sig.full_p$ == 0);
};--while
};--mon_rx_data_out_tcm
The input collection requires to wait for start bit. Then collect a stream of bits and convert it a parallel byte.
At the completion of byte collection, a stop bit check is performed.
mon_rx_data_inp_tcm() @sig.clk_r_ev is {
wait true (sig.rst_p$ == 0);
message(NONE, "mon_rx_inp_tcm reset wait ended ", name);
while(TRUE) {
--wait for start bit
var ck_en_cnt : byte = 0;
while(ck_en_cnt < 3) {
wait true (sig.ck_en_p$ == 1);
ck_en_cnt=sig.rx_in_p$ == 1 ? ck_en_cnt : ck_en_cnt+1;
wait true (sig.ck_en_p$ == 0);
};--while
--serial data capture
var data_bit : bit;
var data_inp : byte = 0;
var data_bits_l : list of bit;
for j from 0 to 7 do {
for i from 0 to 2 do {
wait true (sig.ck_en_p$ == 1);
wait true (sig.ck_en_p$ == 0);
if(i == 1) then {
data_bit=sig.rx_in_p$;
};
};--for
data_bits_l.add(data_bit);
};--for
unpack(packing.low, data_bits_l, data_inp);
message(NONE, "%s mon_rx_inp_tcm d_inp %02x", name, data_inp);
scbd_inp.add(data_inp);
mon_rx_data_cmp();
--wait for stop bit
wait true (sig.ck_en_p$ == 1);
check that sig.rx_in_p$ == 1 else dut_error(
name, " mon_rx_inp_tcm stop bit error"
);
wait true (sig.ck_en_p$ == 0);
};--while
};--mon_rx_data_inp_tcm
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