ASIC/FPGA Design and Verification Out Source Services
Divide By Constant
- Recently I have been asked by a colleague to find a good solution for a divide by 7 VERILOG implementation.

- After some searching in the WEB, I found some explanation from Brown University.
2^P + R = 0 mod C and R*n<2^P
2^11 + 3=2051 =7*293
multiply by 293 and shift right 11 times.
293=256+32+4+1 So no need for real multiplier.
proof is given for divide by 10
multiply n<2^31 by (2^31+2)/10 then right shift 31 positions
floor[n*((2^31+2)/10)* 1/(2^31)]=
floor[n/10+2*n/(10*2^31)]
where floor is defined
floor produce a quotient that has been truncated toward negative
infinity; that is, the quotient represents the largest mathematical integer
that is not larger than the mathematical quotient.
Please note that I included a nice option to search my site (at bottom of the page). It offers a tool with some keywords to look for in my site, but you can try also your own.
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