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RTL Changes to facilitate post synthesize simulation

In general LEON can be synthesized easily. There are two issues that one may consider to change:

1. I/O - Some of them are in two different entities and therefor the XILINX mapper can not use hierarchal net-list. I needed to use the switch (-ignore_keep_hierarchy).
2. In the test-bench, the LEON is instantiated with I/O sorted by order and it is easier by name method. In the post synthesize net-list, the I/O order can not be controlled.

Example:
before
leon0 : leon port map (rst, clk, sdclk, plllock,error, address, data, ...
after
leon0 : leon_pci port map (
resetn => rst,
clk => clk,
pllref => sdclk,
plllock => plllock,
errorn => error,
...

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