ASIC/FPGA Design and Verification Out Source Services
Final steps required for generating code coverage with NCSIM simulator using GUI mode
- In this short memo, I'll show the final steps required for generating the code coverage report. I get into trouble every time I do that and decided: it better be on my web site.
- At this stage you have specified coverage in NCELAB command (see below how to do it) and have many tests results from regression. You need to merge all files into one file data base.This is accomplished using the following command and script.iccr codecov/iccr_regression_load.cmdwhere the file -iccr_regression_load.cmd- contains the following iccr commands:
load_test bg.kren.10_08_08/chain_0/reg_1_tests/*/run_*/cov_work/design/test*
union all_tests
- Next step is to load all regression test results. The tools saves the all data merged info into a file named all_tests as default. Read the file and launch the GUI using the following command and script:iccr codecov/iccr_regression_view.cmdwhere the file -iccr_regression_view.cmd- contains the following iccr commands:
load_test bg.kren.10_08_08/chain_0/reg_1_tests/random_short/run_9/cov_work/design/all_tests
view_graphics
- Note the location of the file all_tests was found simply by using the linux find command.
- NCELAB control:
ncelab -COVFILE codecov/elab.cf .... where the file elab.cf contains the following commands:
select_coverage -bet
set_glitch_strobe
set_assign_scoring
set_branch_scoring
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Make sure that your ncsim.log contains the code coverage message:
End-of-test operations are completed
See ./cov_work/design/test/icc.com file for message(s) on coverage constant object marking
coverage setup:
workdir : ./cov_work
dutinst : :(PM_TB_LIB.enet_tb(top))
design : design
testname : test
coverage files:
model(design data) : ./cov_work/design/292136df_00000000.ucm
data : ./cov_work/design/test/icc.ucd
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