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Miscellaneous Digital HW Tips

To synchronize or not to synchronize an asynchronous global reset input:

1. The reset signal is usually as loaded as your clock net. If you don't take care on your clock net, it will soon bite you as this net is clocking your design every cycle, when clock is enabled.
2. The reset is active usually once right after power up, so a timing error would not happen so frequent as if it were to exist on the clock. When it does happen, however, your system may "go south" after power up. The reset signal is usually highly loaded. In my opinion it is a very good practice to synchronize it to the clock, if it is asynchronous.
3. The reset itself should be synchronized. Suppose FF_A drives FF_B. When the reset of FF_A is negated, its output will change. For an asynchronous reset, FF_B may go metastable, depending on the relation bewteen the edges of reset negation and clock rise.
4. Reduce load: Sometimes not all of the design modules require the reset activation on the very same cycle. The control of the design usually do, but when it comes to the assorted stages of a pipe line data path, one may consider having reset the assorted modules Not on the very same cycle.
5. Question: assuming a Reset signal needed to get to all the design ( User Global reset) should I insert this signal into a BUFG? press here to see details

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