ASIC/FPGA Design and Verification Out Source Services

Verification code development Plan for the VHDL IP stack project

1. When creating any program one has the choice to write the entire project and than start a long debug process or do it in several steps. I prefer the later.


2. The goal of the project is to verify a VHDL IP stack, a DUT, which handles ICMP (ping). VHDL IP project
   The verification environment should support multiple network nodes sending ping. So the DUT will process pings from many sources, arriving when DUT is busy or free.


3. The first part to be coded is the transmission. At the end of this step the verification environment will be able to transmit one ICMP request correctly . Especially is the checksum, total length and CRC fields of the ICMP, IP and frame, have to be verified. Note that the DUT was tested using a small VHDL test-bench, which tested these assorted functions in the DUT. As an example is the dedicated ETHERNET CRC test-bench at CRC . The benefits of this specman verification environment will show up when multiple piped requests will be sent and the DUT response will be tested and verified.


4. In order to check the DUT's response, a monitor has be used in the second step. The monitor is needed to detect if the DUT sends an ARP request. In that case the environment should respond to it.


5. Last this eVC should be flexible enough to allow multiple instantiation of network nodes that sends ping response and can distinguish between the assorted responses on the line.This is done in the last step of the code development.

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