ASIC/FPGA Design and Verification Out Source Services

Hierarchy finder for VERILOG and VHDL mixed code PERL script

1. It is required often to have the hierarchy of a design. This information can save engineer and -license of HDL tools- effort in large designs.


2. This script is aimed to find the hierarchy of designs that include either VERILOG, VHDL or mixed code.


3. The script is run this way:
   perl hier_n.pl test_bench.v [top_level_module]


4. If the optional test bench top level name is not given, all modules are printed with first find first print order.


5. Once you know test bench top level name and enter it to the script, the script will print all design hierarchy top down order.


6. The first parameter is mandatory. It is a list of files to be read and used to create the hierarchy report.


7. Examples of print logs are shown below. The first one is not ordered and the seconded is ordered.


8. perl hier_n.pl tb_ip.f
   module name:: child module name;child instance name

ip_stack_tsb:: sync_wr_mem;u_smem stack;u_dut rx_gen;u_rx_gen
rx_gen::
stack:: ethernet;mas ethernetsnd;massnd arp;arptable arpsnd;arpsender internet;networklayer internetsnd;networklayersend udp;udptransportlayer icmp;icmptransportlayer bufg;rx_clkbuff bufg;tx_clkbuff
ethernet:: crcgenerator;crcgenethrec
crcgenerator::
ethernetsnd:: crcgenerator;ethernetsendcrcgen
arp::
arpsnd::
internet::
internetsnd::
udp::
icmp::
bufg::
memory::
sync_wr_mem::


9. perl hier_n.pl tb_ip.f ip_stack_tsb
   Note that once you entered the top level, the report is ordered from top down and the number of leading spaces is in accordance with the hierarchy level.

ip_stack_tsb
 sync_wr_mem;u_smem
 stack;u_dut
  ethernet;mas
   crcgenerator;crcgenethrec
   crcgenerator;ethernetsendcrcgen
  ethernetsnd;massnd
   crcgenerator;ethernetsendcrcgen
  arp;arptable
  arpsnd;arpsender
  internet;networklayer
  internetsnd;networklayersend
  udp;udptransportlayer
  icmp;icmptransportlayer
  bufg;rx_clkbuff
  bufg;tx_clkbuff
 rx_gen;u_rx_gen


10. New:The script also prints per each file, which was read, the modules found in this file.


11. The script was run on a design that is available on this web site. Note this site contains many useful information like VHDL and VERILOG design and test benches as well as system C and specman and scripts. Just use the search option available almost on any page to find you way round the site.


12. No supported: I do not support a multiple instance of the kind:
    example:
    A_mod Inst[3:0] ( .i(i_arry), .... .o(o_array));
    This results in four instance with first getting i_arry[0:0] and o_arry[0:0] etc.
    


13. go to the script script


14. Sometimes the time, that took the perl script, to finish its job, is interesting. So one can add the following commands, before test end:
    

#print perl time
$t=time - $^T;
print("$t\n");


15. This is what I do at work using ncsim:
    Create source list, using ncls utility.
    Extract all files from the ncls log.
    Remove non vhdl and non verilog files, which the script does not know how to process.
    Start the script.
    
    ncls -source -vhdl -SNAPSHOT PM_TB_LIB.UART_TB_CFG
    grep "\.v" ncls.log > v_list.txt
    vi v_list.txt +/"\.vunit"
    perl ~/bin/hier_n.pl v_list.txt uart_tb
    
    In one case ncls failed to find the snapshot. The solution was to run with explicit directions as shown below:
    
    /tools/bin/ncls -hdlvar db_ip_gt/hdl.var -cdslib db_ip_gt/cds.lib -source -verilog -snapshot my_snap.sys -64bit
    
    If you don't know the snapshot name, this may work for you (running ncls and on its log, opened from within vim):
    
    For QUESTA / MTI simulator (to generate file list) do:
    write report file.list
    
    
    #!/bin/perl
    
    #ncls -source
    #:% !perl ~/bin/vim_ncls_source.pl
    
    while () {
      chomp($_);
      if($_ =~ /(^[ \s\t]*)(\/.*\.[a-zA-Z0-9]*)( \[lines.*)*/) {
        print("$2\n");
      }
    }
    
    


16. A script, that extracts file list from synopsys VCS report is shown in the following link.
    

Home	Extending the systemc example from cadance of producer consumer. How to grep all loaded files in specman or ncsim.