ASIC/FPGA Design and Verification Out Source Services

Receive I/O description

Signal	Description
Clk_48	Input 48MHz clock
Rst	Input reset
usb_reset	Input internal reset
tx_oe	Input usb TX output enable
Dp	Input data plus
Dm	Input data minus
rx_phase_cnt[7:0]	Output internal phase recovery error
rx_stuff_cnt[7:0]	Output number of bit stuff errors
rx_err	Output receive error
rx_do[7:0]	Output data to usb function
rx_va	Output receive valid
rx_vl	Output receive frame valid
dp_s	Output data plus synchronized
Sie0	Output sie0

The following waveform describes the interface:

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The IO is described at : PHY IO description. The block diagram of PHY top is: PHY top block diagram. The description of the block usb_rst usb reset block. The description of the block usb_tx usb transmit. The sedcription of the block usb receive usb receive.

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