ASIC/FPGA Design and Verification Out Source Services

VHDL IP Stack Verification block diagram

Verifying the VHDL IP stack using specman:

1. The following describes a general block diagram for verification of the STACK IP.




2. The interface to the DUT both in transmit and receive side is 4 bit MII.


3. On the receive side a sequence drives packets to the DUT via a BFM.


4. The generation flow is as follows:
   The environment generates a ping request. Than network layer data is added. Based on formerly prepared ICMP ICMP and network data, a physical layer frame is built and sent via MII.
   The DUT may issue an ARP request. In that case the environment will check its validity and respond it.
   The environment also checks the ICMP response coming out from the DUT.
   


5. The data item used in this verification component represents an ETHNERNET frame.
   A structure to capture the ICMP assorted fields and a structure for ARP ones are defined.
   Finally a structure to be used by the sequence driver, which also uses the above two structures as well as other fields to drive data to the DUT, is defined.
   


6. The next page describes the assorted files in this project: files


7. Verification code development Plan for the VHDL IP stack project is at the following link: V plan


8. How to compile the specman code and the VHDL DUT and test-bench code is described in the following guide. The compilation, elaboration and simulation is done using NCVHDL simulator. run script


9. IP frame checksum calculation is explained in specman method that calculates the IP header checksum .
   
10. To go back to the VHDL IP main page: main .
    

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