ASIC/FPGA Design and Verification Out Source Services

AHB and APB Generator

General:
Presently all I have, as an RTL code, is the APB slave, which was orignally written in verilog.
The file name, which is located at the download area, is APB_slave.v.
The effort to convert the LEON special VHDL code style, is time consuming. Some of the reasons are the usage of records, which are used for I/O and variables. In order to quickly translate the VHDL to verilog, I'll synthesize the code and will only have to translate the test bench, which should fairly easy.

I would be happy to offer my services. Call ASAP !

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simualation Control from CPU in SOC

synthesis verilog of AHB master synthesis verilog of APB master simulation using verilog of AHB and APB masters Download Area