ASIC/FPGA Design and Verification Out Source Services

1. The entire project is to help to create small test benches, where AHB or APB generators are required. The project started by taking some components from the free LEON project. Using the AHB and APB masters as building blocks, helped to build the environment quickly in VHDL.


2. To have the same capability in VERILOG, however, it was quite challenging. The VHDL code is written using records and variables, which makes it difficult to translate into VERILOG by simple means such as VI or PERL script.


3. In order to take advantage of the fact that LEON masters are fully able to synthesize, the VHDL assorted modules are synthesized. Then VERILOG net-lists are generated, using netgen from Xilinx.


4. The VHDL test bench is re-written in VERILOG. The design is than simulated using the free VERILOG simulator icarus.


5. The simulation requires Xilinx's simprim library. The global reset module namely: glbl.v is also needed and is included in the compilation script.



6. An AHB VHDL project, was made of two AHB masters, one arbiter, one AHB to APB bridge and one simple APB slave. If you are interested in this project as a graduate project, contact me via mail and put in the subject: non free AHB project.

I would be happy to offer my services. Call ASAP !

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