ASIC/FPGA Design and Verification Out Source Services

One clock domain register (made by Flip-Flop devices) FIFO

1. The I/O interface is quite the same as any other FIFO design: clock, reset, data, and flags:


1. input ck, rs; //clock and reset
   
2. input [`WIDTH-1 : 0] wr_d; //write data
   
3. input wr_en; //write enable
   
4. output full; //full
   
5. output hfull; //half full
   
6. output [`WIDTH-1 : 0] rd_d; //read data
   
7. input rd_en; //read enable
   
8. output empty; //empty
   


2. The flags are implemented with a set condition and keep set condition.


1. empty <= ( empty & ~wr_en) |
   
2. (~empty & ~(|rd_ptr) & rd_en & ~wr_en);
   
3. full <=
   
4. (~full & (rd_ptr == (DEPTH-2) && wr_en && ~rd_en)) |
   
5. (full & ~rd_en);
   
6. hfull <= (rd_ptr >= (DEPTH/2));
   

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