ASIC/FPGA Design and Verification Out Source Services
Test Bench for Register FIFO
- The main features of the test bench are:
- Clock and Reset Generation
- Random Stimuli according seed, which is set by a PERL script
- Simulation Log Report Generation
- VCD Wave Generation
- Simulation stop via finish command
- Random delay between write and read transactions to allow full and empty events to happen
- Count pattern write
- Read Results Print to log to allow check by script
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