ASIC/FPGA Design and Verification Out Source Services

Test Bench for Register FIFO

1. The main features of the test bench are:
2. Clock and Reset Generation
3. Random Stimuli according seed, which is set by a PERL script
4. Simulation Log Report Generation
5. VCD Wave Generation
6. Simulation stop via finish command
7. Random delay between write and read transactions to allow full and empty events to happen
8. Count pattern write
9. Read Results Print to log to allow check by script

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FIFO Test-Bench Regression perl Script

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