ASIC/FPGA Design and Verification Out Source Services

How to drive a specman state (enumerated type) to wave, to aid debug.

1. Suppose you have a state machine with a type like this:
   
   type sbt_fsm_state_t : [ADDR_WAIT, DATA_LOAD, PARITY_LOAD, HOLD_STATE, BUSY_STATE];
   


2. In my case a monitor had such a state with much more states. To facilitate the debug, I wrote the state to waves with its meaningful names.


3. To do that one first has to declare a string variable in the verilog bench.
   
   reg [14*8:0] spc_usb_2G_mon;
   //for debug
   initial begin
     spc_usb_2G_mon[ 7:0]=8'h61;
     spc_usb_2G_mon[15:8]=8'h62;
   end
   
   


4. Next comes the specman side. First in your signal map instance add the string port:
   
   //spc debug - drive state to wave
   spc_usb_2G_tms_mon: out simple_port of uint(bits:113) is instance;
   keep bind(spc_usb_2G_tms_mon, external);
   
   


5. Add this method and use it to drive the debug port:
   
   
   1. str_to_uint_113(st : usb_2G_states_t) : uint(bits:113) is {
   2.   var bytes_l := appendf("%s", st).as_a(list of byte);
   3.   bytes_l=bytes_l.reverse();
   4.   result=0;
   5.   for each (b) in bytes_l {
   6.     result[8*index+7:8*index]=b;
   7.   };//for each (b) in bytes_l
   8. };
   
   
   Use it:
   
   sig.spc_usb_2G_mon$=str_to_uint_113(usb_2G_state);
   

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