ASIC/FPGA Design and Verification Out Source Services

FFT system C project - 8 point FFT using DIT algorithm.

1. The first stage of the FFT, requires addition and subtractions only (twiddle factors of 1 or -1.


2. The second stage twiddle factors are 1, -1, j or -j. Again this stage, as the former one, does not have fractional twiddle factors.


3. Last stage has twiddle factors of the combination of 1+j, -1+j, etc ...


4. The fractional .070710678 is multiplied by 8 and rounded to 6, which also reduces the accuracy. In another example a multiply factor of 16 is used. This improves the accuracy as the number 0.070710678 is now represented by two digits of precision (11 instead of 6). FFT accuracy issues


5. In the code therefor you either see a multiplication of 8 (twiddle factor of 1, -1, j or -j) or 6.


6. A complex multiplier (two-dimensional Cartesian coordinate is used at both of its inputs and outputs) using only three scalar multipliers, to save chip area, is also available on this site:
   from:


7. Return to the FFT main page. FFT main page .

Please let me know what you think on this FFT work.

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