ASIC/FPGA Design and Verification Out Source Services
The inputs to the CRC7 module in assorted cases such as command and response of 48 bits and response of 136 bits is explained at:CRC7 input description.
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Please note that a newer version of the SD slave exists. It supports Samsung flash instead of xilinx ROM.
link to newer version
- Input:rst Asynchronous active high reset
- Input:clk Input clock
- Input:clr Synchronous clear
- Input:din Serial data input
- Input:cen Clock enable
- Output:crc 7 bits crc outputs
The CRC is calculated using the seven registers q6 to q0.
The assign statements implement the polynomial of x(7)+x(3)+1.
The VERILOG code can be downloaded from the download area (sd_slv_cr7.v).
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